PEDGE_DRV_EN=Val_0x0, CMD_CONFLICT_CHECK=Val_0x0, NEDGE_SMPL_EN=Val_0x0, SW_CG_DIS=Val_0x0
SDMMC Host Controller Control Register
| CMD_CONFLICT_CHECK | Command Conflict Check. This bit enables command conflict check. 0 (Val_0x0): Disable command conflict check 1 (Val_0x1): Check for command conflict after 1 card clock cycle |
| SW_CG_DIS | Internal Clock Gating Disable Control. This bit must be used to disable the SDMMC module internal clock gating when required (disabled clocks are not gated). The clocks to the core (except HCLK) must be stopped when programming this bit. 0 (Val_0x0): Internal clock gates are active and clock gating is controlled internally 1 (Val_0x1): Internal clock gating is disabled, clocks are not gated internally |
| PEDGE_DRV_EN | Launches CMD/DATA with respect to positive edge of CCLK_TX for Low-Speed SDR only support. 0 (Val_0x0): Launches CMD/DATA with respect to negative edge of CCLK_TX 1 (Val_0x1): Launches CMD/DATA with respect to positive edge of CCLK_TX |
| NEDGE_SMPL_EN | Samples CMD/DATA with respect to negative edge of CCLK_RX for Low-Speed SDR only support. 0 (Val_0x0): Samples CMD/DATA with respect to positive edge of CCLK_RX 1 (Val_0x1): Samples CMD/DATA with respect to negative edge of CCLK_RX |